1. Field of the Invention
The present invention relates to a device and method for testing a semiconductor process, more particularly, to a semiconductor device and related method for testing a semiconductor process failure rate using a differential testing configuration.
2. Description of the Prior Art
In the semiconductor industry, the purpose of DFM (Design for manufacture) is to monitor semiconductor nanometer processes for understanding process failure, to reduce design sensitivity in manufacturing variations, and to create accurate yield models. Therefore, semiconductor process controls in the nanometer area have comparatively more difficult challenges because of its sensitivity on product yield. A major challenge in DFM is how to evaluate yield loss, and to create an accurate yield model. According to the prior art, the monitoring process measures a large number of semiconductor resistors to obtain absolute value of the overall resistance for process monitoring purposes. There are several conventionally existing methods to perform process monitoring. Please refer to FIG. 1. FIG. 1 shows a conventional Kevin structure to measure resistance. In the Kevin structure, one resistor 14 requires a first pin 10, a second pin 12, a third pin 16, and a fourth pin 18 as test points in determining its resistance. Therefore the testing structure in FIG. 1 requires a plurality of pins to measure the resistance of each individual component (e.g., the resistor 14). Using the conventional Kevin structure, only the exact resistance value of each single component can be measured. Another conventional testing scheme is disclosed in patent application US 2005/0090922 A1, where a mesh type circuit is taught to measure exact resistance value of a single component.
Furthermore, if a chain of under test devices (DUT), such as a chain of N resistors, has been tested, there will have three possible measurement results as shown in FIG. 2, FIG. 2 is a diagram illustrating the measurement results according to the prior art testing method. The first one is the measurement result is within an acceptable range 21, which is caused by process variation. The second one is the measurement result is within a soft fail areas 22. The third one is the measurement result is in a hard fail areas 23. Because the measurement result is the total resistances of the chain of N resistors, when the measurement result is located in the soft fail areas 22, it is hard to determine that what problem was happened to the chain of N resistors. For the example, there may have one resistor be almost failed that to increase the total resistances locate within the soft fail area 22, or there may be a soft fail occurred to the chain of N resistors. Furthermore, the former one can be very dangerous when in using, although the measurement result is located in the soft fail area 22. Therefore, the above-mentioned prior art testing schemes are unable to determine if a non-ideal measurement result is caused by the soft fail or a process failure in a semiconductor process.